Half Subtractor and Full Subtractor VHDL Simulation Code

Experiment: Write a VHDL code for half subtractor and full subtractor and simulate the code.

Introduction:
To develop code for half subtractor and full subtractor. Simulate the code in the software.

Material required:
1. Xilinx Software Loaded PC = 1 Set.
2. Print = 1.

Description:
1. Theory
2. Algorithm
3. Description
4. VHDL Code Writing
5. Compile and Run program.

Theory:
The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two outputs. The adder is used to perform OR operation of two single bit binary numbers.

ALGORITHM:
1. Define Library functions.
2. Declare Entity and Architecture.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

DESCRIPTION:
The augent and addent bits are two input states, and ‘carry’ and ‘sum ‘are two output states of the half adder.

Half-subtractor circuit

TRUTH TABLE

VHDL Code for a Half-Subtractor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library ieee;
use ieee.std_logic_1164.all;
  
entity half_sub is
    port ( a,b : in std_logic;
           dif,bo: out std_logic );
end half_sub;
architecture sub_arch of half_sub is
  begin
     dif <= a xor b;
     bo <= (not a) and b;
end sub_arch;

Full-Subtractor
The Half Subtractor is used to subtract only two numbers. To overcome this problem, a full subtractor was designed. The full subtractor is used to subtract three 1-bit numbers A, B, and C, which are minuend, subtrahend, and borrow, respectively. The full subtractor has three input states and two output states i.e., diff and borrow.

Full-Subtractor circuit:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_sub is
   port(a,b,c: in bit; sub, borrow:out bit); 
end full_sub; 
 
architecture data of full_sub is
begin
   sub<= a xor b xor c; 
   borrow <= ((b xor c) and (not a)) or (b and c); 
end data; 

TRUTH TABLE

VHDL Code for a Full-Subtractor
VHDL program to build half and full-subtractor circuits. Verify the output waveform of program (digital circuit) with the truth tables for the half and full-subtractor circuits.

Half-subtractor Output

Full-subtractor Output

Questions with answers:
1. What is the half-subtractor?
Ans: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits.

2. What is the Full-subtractor?
Ans: A full subtractor is a combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs.

3. What is half-subtractor boolean expression?
Ans: Difference = A ⊕ B
Borrow = A’ B

4. What is Full-subtractor boolean expression
Ans: D = A ⊕ B ⊕ Bin
Bout = A’ Bin + A’ B + B Bin

Half Subtractor Video Tutorial: