AND Gate Simulation in Xilinx using VHDL Code

AND Gate Simulation in Xilinx using VHDL Code

Write a VHDL code for logic gates (AND gate, OR gate) and simulate the code.
Introduction:
To Develop code for logic gates. Simulate the code in the software.

Required Components:
1. Xilinx Software Loaded PC = 1.
2. Printer = 1.

Procedure for doing the exercise/experiment:

1. Theory
2. Algorithm
3. Description
4. Flow Chart
5. VHDL Code Writing
6. Compile and Run program.

Theory:

A test bench is a virtual environment used to verify the correctness of a design or model called “design under test”. A test bench has four components…

1. Input: the signals needed to perform work
2. Procedures to do: the tasks or processes that will transform the input into the output
3. Procedures to check: the processes that determine that the output meets the standards
4. Output: The output signals produced from the workbench

ALGORITHM:

1. Define Library functions.
2. Declare Entity and Architecture.
3. Describe functionality.
4. End source code and define Test Bench.
5. Compile and Run program

Description:
Develop a VHDL test bench code for testing any one of the simple gate. Simulate the test bench code in the HDL software.

Flow Chart:

Code Listing (AND gate program)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gate is
    Port ( a: in  STD_LOGIC;
           b: in  STD_LOGIC;
           c: out  STD_LOGIC);
end gate;

architecture Behavioral of gate is
begin
c <= a and  b;
end Behavioral;

AND Gate Output Waveform:

Code Listing ( OR gate program)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gate is
    Port ( a: in  STD_LOGIC;
           b: in  STD_LOGIC;
           c: out  STD_LOGIC);
end gate;

architecture Behavioral of gate is
begin
c <= a or b;
end Behavioral;

OR Gate Output Waveform:

Result:
Thus a test bench for the given logic gate was simulated.

Questions with answers:
1. Software name? Ans: Xilinx Software
2. SOP Means? Ans: Sum of Product
3. How many Types of VLSI Programming Language?
(a) VHDL (Very High speed Hardware Description Language)
(b) Verilog Type
4. What is AND gate Boolean Expression? Ans: Y = A.B
5. What is OR gate Boolean Expression? Ans: Y = A+B

AND Gate Video Tutorial: