Shift Register Animation

Shift Register Animation:-

The 74HC164 is high-speed CMOS device fabricated with silicon gate CMOS technology.

It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL (Transistor Transistor Logic) while maintaining the CMOS low power dissipation.

The 74HC164 is a high-speed 8-Bit Serial-In/Parallel-Out Shift Register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock.

The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock.

An input protection circuit insures that 0V to 6V can be applied to the input pins without regard to the supply voltage. Regulated power supply of this IC VCC is 3.3 ± 0.3V or 5.0 ± 0.5V Dc.

Shift Register Blockdiagram:

The normal range of clock pulse rating is 200 Hz to 1Khz.

The animation of the picture function setting is A and B of the AND Gate data inputs are HIGH and MR (Master Reset) is connected to the 5v supply, then logically LEDs are ON one by one with clock pulse.

The Resistors are connected in this circuit is original colour coded type and calculate by resistor code value.

When the reset switch is the output LEDS are goes to ON logically, after reset switch is closed all LEDS goes to OFF.

NOTE: The input of AND gate A,B are in HIGH state.

A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

The Data A and B input of the shift register is HIGH states into Low level then LEDs goes off one by one fron Q0 to Q7.

OPERATION:-

74HC164 are 8-bit edge-triggered shift registers with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either input can be used as an active HIGH enable for data entry through the other input.

Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND GATE of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge.

Features:-

• High Speed: f MAX =175MHz at VCC=5V
  Low power dissipation: ICC=4μA (max.) at TA=25°C
  High noise immunity: VNIH=VNIL=28% VCC(min.)
  Power down protection provided on all inputs
  Low noise: VOLP=0.8V (max.)
  Pin and function compatible with 74HC164