FETs (FIELD EFFECT TRANSISTOR) are majority-charge-carrier devices. The device consists of an active channel through which majority charge carriers, electrons or holes, flow from the source to the drain. Source and drain terminal conductors are connected to the semiconductor through ohmic contacts. The conductivity of the channel is a function of potential applied across the gate and source terminals.


The FET’s three terminals are Source (S), through which the majority carriers enter the channel. Conventional current entering the channel at S is designated by IS Drain (D), through which the majority carriers leave the channel. Conventional current entering the channel at D is designated by ID. Drain to Source voltage is VDS. Gate (G), the terminal that modulates the channel conductivity. By applying voltage to G, one can control ID. The FET, which has Source lead S, Gate lead G, and Drain connection D.
The path for current is from Source to Drain through the semiconductor material, this path being termed the channel. With the N-channel FET, the carriers are electrons. The Source is connected to negative of the supply, and Drain to positive. P-type gates are formed on the N-type channel, providing PN junctions.When these junctions receive reverse bias, areas surrounding them are emptied of electron carriers. These “depletion areas” reduce the width of the carrier channel as at B. As a result there is a drop in the passage of current carriers from Source to Drain.
Increasing the bias causes the depleted regions to extend, and the channel grows smaller, reducing current even further. Eventually the gate can be made so negative that the channel is virtually closed. This is the pinch off region, and current is practically zero.The current from source to drain, and through external circuit items, can therefore be controlled by adjusting the gate voltage. Since the gate to channel junction area is reverse biased gate current is extremely small, and thus the gate input Impedance is very high. Generally, the gate current is negligible.                 


  • Connect   DMM  positive test lead to  GATE
  • ……………DMM Negative test lead to DRAIN Display reading shows 0.715v
  • ……………DMM Negative test lead to SOURCE =display reading shows 0.703v
  • Connect   DMM  Negative test lead to GATE
  • …………..DMM  positive test lead to DRAIN    OL  DMM READING ( OL MEANS OVER LOAD).
  • …………..DMM  positive test lead to  SOURCE OL


  • DMM  positive test lead to   DRAIN
  • DMM  Negative test lead to SOURCE DISPLAY READING 0.090V
  • DMM  Negative test lead to DRAIN    OL  DMM READING ( OL MEANS OVER LOAD)
  • DMM  Positive test lead to   SOURCE   READING 0.090v or (090 mV)

Connect   DMM Negative lead to Shield

  • DMM   Positive test lead to GATE       open or open or ‘1’
  • DMM  positive test lead to DRAIN      OL  DMM READING ( OL MEANS OVER LOAD)
  • DMM  positive test lead to  SOURCE  OL

Verification: If the DMM above reading shows the condition is GOOD.
Verification:  If you get reading in forward bias as 0000 or OL  or 1, and in reverse bias as 0000 (or) low values the FET transistor can be FAULTY and needs replacement.

About the Author


Hello! My Dear Friends. I am Subramanian. I am writing posts on androiderode about Electronics testing and equipments.

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