Experiment: Write a VHDL code for half adder and full adder and simulate the code.

Introduction:
To develop code for half adder and full adder. Simulate the code in the software.

Required Components:
1. Xilinx Software Loaded PC = 1 Set
2. Print = 1

Description:
1. Theory
2. Algorithm
3. Description
4. VHDL Code Writing
5. Compile and Run program.

Theory:
Half adders are a basic building block for new digital designers. A half-adder shows how two bits can be added together with a few simple logic gates. A single full-adder has two one-bit inputs, a carry-in input, a sum output, and a carry-out output.

Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.

ALGORITHM:
1. Define Library functions.
2. Declare Entity and Architecture.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

DESRIPTION:
For adding together larger numbers a Full-Adder can be used. A single half-adder has two one-bit inputs, a sum output, and a carry-out output.

Refer to the truth table below to see how these bits operate. The code creates a half adder. There is also a test bench that stimulates the design and ensures that it behaves correctly.

VHDL Code Half adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_adder is
   port(a,b:in bit; sum,carry:out bit); 
end half_adder; 
 
architecture data of half_adder is
begin
   sum<= a xor b;  
   carry <= a and b;  
end data;

Half  adder Circuit Diagram.

Full adder Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is port
(a,b,c:in bit; sum,carry:out bit); 
end full_adder;
  
architecture data of full_adder is
begin
   sum<= a xor b xor c; 
   carry <= ((a and b) or (b and c) or (a and c)); 
end data;

Full adder Circuit Diagram:

Result:
An half-adder shows how two bits can be added together with a few simple logic gates.
A single full-adder has two one-bit inputs, a carry-in input, a sum output, and a carry-out output.

Half-adder Simulation Output:

Full-adder Simulation Output:

Half Adder Vide Tutorial:

Full Video Tutorial:

Questions with answers:
1. What is Half Adder?
Ans: A half adder is a type of adder, an electronic circuit that performs the addition of numbers.

2. What is Full Adder?
Ans: Full Adder is the adder which adds three inputs and produces two outputs.

3. Which type of Logic gates used in Half Adder?
Ans: one EX-OR gate and one AND gate.

4. Which type of Logic gates used in Full Adder?
Ans: 2 Half Adders and a OR gate is required to implement a Full Adder.

About the Author

Subramanian

Hello! My Dear Friends. I am Subramanian. I am writing posts on androiderode about Electronics testing and equipments.

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